`timescale 1ns/1ps
`include "code\source\P1\interleaver.v"

module tb_interleaver;

// Input
reg clk2;
reg rst_n;
reg din;
reg din_valid;

// Output
wire dout;
wire dout_valid;

interleaver u_interleaver(
                .clk2 (clk2 ),
                .rst_n (rst_n ),
                .din (din ),
                .din_valid (din_valid ),
                .dout (dout ),
                .dout_valid (dout_valid ));

always begin
    #5 clk2 = ~clk2;
end

initial begin
    $dumpfile("./release/test_interleaver.vcd");
    $dumpvars(0, tb_interleaver);
end

initial begin
    clk2 <= 0;
    rst_n <= 0;
    din <= 0;
    din_valid <= 0;
    #10
    rst_n <= 1;
    #10
    din <= 1;
    din_valid <= 1;
    #80
    din <= 0;
    #80 
    din <= 1;
    #80
    din <= 0;
    #80 
    din <= 1;
    #80
    din <= 0;
    #80 
    din <= 1;
    #80
    din <= 0;
    #80 
    din_valid <= 0;
    #1000
    $finish;
end

endmodule
